1. Field of the Invention
This invention relates to a semiconductor memory device and information processing unit and, more particularly, to a semiconductor memory device having a burst mode, in which a plurality of bits of data are consecutively transferred in block in response to an external command, and information processing unit having such a semiconductor memory device.
2. Description of the Related Art
(First Prior Art)
With what is called an I/O common semiconductor memory device in which written data and read data flow along the same data bus, the data bus can be used effectively by setting write latency, being delay time between the inputting of a write command and the writing of data to be written.
FIG. 34 is a timing chart showing how to transfer data in the case of write latency not being set. FIG. 35 is a timing chart showing how to transfer data in the case of write latency being set.
FIG. 34 is a view showing a read-write-read (RD-WR-RD) cycle in the case of burst length being xe2x80x9c2xe2x80x9d and write latency being xe2x80x9c0.xe2x80x9d In this example, an RD command is input in synchronization with the leading edge of the zeroth clock (CLK) shown in FIG. 34(A) (see FIG. 34(B)). With most semiconductor memory devices, certain access time is needed between the inputting of an RD command (CMD) and the sending of data to a bus. In this example, as shown in FIG. 34(C), bits of read data (DATA) Q1 and Q2 are sent to a data bus at the leading edge of the third clock, that is to say, when three clocks have elapsed after the inputting of the RD command.
After the bits of read data are sent, a WR command is input at the leading edge of the fifth clock. The write latency is xe2x80x9c0,xe2x80x9d so bits of written data D1 and D2 are input via the data bus almost concurrently with the inputting of the WR command.
The following RD command is input directly after the WR command, because there exists a delay corresponding to access time between the inputting of an RD command and the sending of data to the data bus and the data bus will not be congested with written data and read data.
As stated above, if the write latency is set to xe2x80x9c0,xe2x80x9d RDxe2x80x94RD cycle time from an RD command to the next RD command is six clocks.
FIG. 35 is a view showing an RD-WR-RD cycle in the case of burst length being xe2x80x9c2xe2x80x9d and write latency being xe2x80x9c3.xe2x80x9d In this example, an RD command is input in synchronization with the leading edge of the zeroth clock shown in FIG. 35(A) (see FIG. 35(B)). As stated above, with a semiconductor memory device, certain access time is needed between the inputting of an RD command and the sending of data to a bus. In this example, the bits of read data Q1 and Q2 are sent to the data bus at the leading edge of the third clock (see FIG. 35(C)).
If write latency is set, there exists a delay between the inputting of a WR command and the inputting of written data. A WR command therefore can be read prior to the sending of read data. In this example, a WR command is input at the leading edge of the second clock.
After the WR command is input and clocks corresponding to the write latency (three clocks, in this example) have elapsed, written data is read. In this example, the bits of written data D1 and D2 are read at the leading edge of the fifth clock.
The following RD command is input directly after the WR command, because, as stated above, there exists a delay corresponding to access time between the inputting of an RD command and the sending of data to the data bus and the data bus will not be congested with written data and read data. Read data corresponding to this RD command is read at the leading edge of the sixth clock.
As described above, if the write latency is set to xe2x80x9c3,xe2x80x9d RDxe2x80x94RD cycle time from an RD command to the next RD command is three clocks. As a result, RDxe2x80x94RD cycle time can be shortened by three clocks in comparison to the above case where the write latency is set to xe2x80x9c0.xe2x80x9d
(Second Prior Art)
Bank interleaving is one of techniques for realizing high-speed access to a semiconductor memory device.
With the bank interleaving technique, the whole of a memory is divided into a plurality of banks and is managed. When a CPU begins to access one of the banks, it begins to access another bank to be accessed next. By the time the first access by the CPU ends, the bank accessed next by the CPU is in a state in which data can already be transferred. The CPU therefore can transfer data without delay.
FIG. 36 is a timing chart showing operation for conventional bank interleaving. FIG. 37 is a view showing an example of circuits for realizing such bank interleaving.
A CLK (clock) input terminal 201 shown in FIG. 37 receives a CLK signal input from the outside. A CMD (command) input terminal 202 receives a CMD signal input from the outside. An ADD (address) input terminal 203 receives an ADD signal input from the outside.
A CLK input circuit 204 provides the CLK signal input from the CLK input terminal 201 to a CMD input circuit 205, ADD input circuit 206, and burst length counter 209.
The CMD input circuit 205 performs waveform shaping on the CMD signal input from the CMD input terminal 202 and provides it to a CMD decoder 207.
The ADD input circuit 206 performs waveform shaping on the ADD signal input from the ADD input terminal 203 and provides it to a burst length judging circuit 208, burst address generating circuit 210, and address importing circuit 211.
The CMD decoder 207 decodes the CMD signal, extracts an RD (read) command, WR (write) command, and NOP (no operation) command from it, and provides them to the burst length counter 209 and address importing circuit 211.
If a command for setting a burst length is input at the time of, for example, starting a device, the burst length judging circuit 208 analyzes the command and judges the set burst length.
When the RD command or WR command is input and a burst transfer is begun, the burst length counter 209 resets the burst address generating circuit 210, counts the burst length in response to the CLK signal, and requests the burst address generating circuit 210 to count up a burst address. Furthermore, when the count reaches the burst length, the burst length counter 209 requests the burst address generating circuit 210 to end generating the burst address.
The address importing circuit 211 refers to the CMD signal supplied from the CMD decoder 207 and, at the time of the burst transfer being begun, selects the ADD signal supplied from the ADD input circuit 206 to output it as an internal address IADD. Furthermore, in order to transfer the second bit and the following lower-order bits, the address importing circuit 211 selects output from the burst address generating circuit 210 and outputs it as the internal address IADD.
Now, operation for the above conventional bank interleaving will be described with reference to FIG. 36.
It is assumed that a device is started, that an MRS (mode register set) command for setting a burst length is input to the CMD input terminal 202, and that data showing the burst length to be set is input to the ADD input terminal 203. Then the CMD decoder 207 recognizes that a request to set the burst length was made and informs the burst length judging circuit 208 of it.
The burst length judging circuit 208 refers to data supplied from the ADD input circuit 206 and judges the burst length to be set. For example, if a request to set a burst length to xe2x80x9c4xe2x80x9d is made, the burst length judging circuit 208 recognizes it and informs the burst length counter 209 of it. As a result, the setting of burst length will be completed.
In this state of things, it is assumed that an RD1 command to request a burst transfer with a predetermined bank as a target (see FIG. 36(B)) is input to the CMD input terminal 202 at the zeroth leading edge of a CLK signal shown in FIG. 36(A). Then the CMD decoder 207 receives this signal via the CMD input circuit 205, recognizes that an RD command was input, and informs the burst length counter 209 and address importing circuit 211 of it.
The burst length counter 209 informs the burst address generating circuit 210 that a request for a burst transfer was made, and causes it to set a leading address for the burst transfer.
The burst address generating circuit 210 obtains a leading address for the burst transfer from the ADD input circuit 206 in response to the request from the burst length counter 209, counts up an address in response to a request from the burst length counter 209 to count up, and provides it to the address importing circuit 211 as a burst address (BADD).
The address importing circuit 211 obtains the leading address for the burst transfer directly from the ADD input circuit 206 and outputs it as an internal address IADD. Furthermore, in order to transfer the second bit and the following lower-order bits of data, the address importing circuit 211 selects the BADD output from the burst address generating circuit 210 as an address and outputs it as the internal address IADD.
Bits of data will be read from a series of addresses generated in this way and be output consecutively to the outside (see FIG. 36(C)).
In the above example, the burst transfer is requested by the RD1 command. Therefore, after predetermined access time has elapsed, bits of data Q11 through Q14 will be read from cells (not shown) and be output.
(Third Prior Art)
To read data from or write data to a semiconductor memory device, addresses to be accessed must be specified.
With a semiconductor memory device having a burst transfer mode, specifying only the leading address of consecutive addresses will enable access to all of them.
With some semiconductor memory devices having such a burst transfer mode, the burst length of data to be written can be set. FIG. 38 is a view for describing the operation of such a semiconductor memory device. It is assumed that the maximum physical burst length for this semiconductor memory device is xe2x80x9c4.xe2x80x9d
It is assumed that a WR1 command to request writing (see FIG. 38(B)) is input and that VW=1 (burst length=1) (see FIG. 38(D)) is input from an address input terminal as a variable write (VW) signal for specifying the burst length. In this case, they are input in synchronization with the zeroth leading edge of a clock (CLK) signal shown in FIG. 38(A).
Then after time corresponding to latency (see FIG. 38(C)) has elapsed, bits of data D11 through D14 are read from the DATA input terminal, which can include data D11-D14, D21-D23 and D31-D34. In this example, the burst length is set to xe2x80x9c1,xe2x80x9d so the bit of data D11 will be sent only to the internal data bus #1 of internal data buses #1 through #4 (FIGS. 38(E) through 38(H)).
The bit of data D11 sent to the internal data bus #1 is stored in a predetermined bit at a predetermined address.
When time corresponding to a bank access interval (see FIG. 38(B)) has elapsed after the WR1 command being input, a WR2 command is input in synchronization with the second leading edge of the CLK signal. After time corresponding to the latency has elapsed, bits of data D21 through D24 and VW=4 are input. As a result, the bits of data D21 through D24 are sent to the internal data buses #1 through #4 respectively. The bits of data D21 through D24 sent to the internal data buses #1 through #4 in this way are stored in predetermined bits, respectively, at consecutive addresses.
When time corresponding to the bank access interval has elapsed after the WR2 command being input, a WR3 command and VW=2 are input. As a result, bits of data D31 and D32 are sent to the internal data buses #1 and #2 respectively.
The bits of data D31 and D32 sent to the internal data buses #1 and #2 in this way are stored in predetermined bits, respectively, at consecutive addresses.
By the way, in the first prior art, a case where a burst length is xe2x80x9c2xe2x80x9d was described as an example. In many cases, however, this value can be set freely.
However, a change in a burst length can lead to a change in the optimum value of write latency. Conventionally, write latency has not changed with a change in a burst length.
As a result, a change in a burst length can make it impossible to perform optimum write operation.
In the second prior art, an interrupt during a burst transfer has been enabled. That is to say, if another command is input during a burst transfer, execution of a command which is being executed at that time is stopped to preferentially execute the last command.
A concrete description of this is as follows. It is assumed that an RD2 command shown in FIG. 36 is input and that an RD3 command is input during the transfer of data corresponding to the RD2 command. In this case, when the transfer of a bit of data Q22 corresponding to the RD2 command is completed, interleaving is performed and the transfer of a bit of data Q31 corresponding to the RD3 command is begun.
To permit such interleaving, however, a command newly input must also be checked during a burst transfer. Moreover, if a request for a burst transfer is made, the process of selecting one of an ADD from the ADD input circuit 206 and BADD from the burst address generating circuit 210 must be performed. This will need the above judging process, which makes it impossible to ensure a sufficient margin for high-speed operation.
In addition, usually semiconductor memory devices have a data bus of bit width corresponding to the maximum burst length that can be set. For example, if the maximum burst length is four bits, then most semiconductor memory devices have a data bus with a width of four bits.
By the way, if a burst length is set to four bits, data should be transferred during time needed for sending 4-bit data (2 CLKs, for example). If a burst length is set to two bits, data should be transferred during time needed for sending 2-bit data (1 CLK, for example). Therefore, if the minimum burst length is set, it is difficult to ensure a margin for operation, resulting in unsuitableness for high-speed operation.
In the third prior art, with not a few semiconductor memory devices having a plurality of DATA input terminals, the DATA input terminal group is divided into a high-order bit group and low-order bit group and burst lengths for them are set independently of each other.
In these semiconductor memory devices, a request to write data only to one of a high- and low-order bit group can be made. Conventional semiconductor memory devices have no means to prohibit writing the data to the other bit group, so unnecessary data will be written.
Furthermore, when a first write command is input, not a few semiconductor memory devices with latency for write operation hold data without writing it to a cell. When a second write command is input, they write the data corresponding to the first write command to a cell.
If tests are made to check whether or not the write operation of these semiconductor memory devices is normal, a write command must be issued twice to cause them to write data to a cell. As stated above, conventional semiconductor memory devices have no means to prohibit writing data. Therefore, writing performed in compliance with the first write command can interfere with writing performed in compliance with the second write command. Eliminating this interference will make the tests troublesome.
The present invention was made under the background circumstances as described above. That is to say, an object of the present invention is to provide a semiconductor memory device which can set optimum write latency according to a burst length.
Another object of the present invention is to provide a semiconductor memory device which enables high-speed operation.
Still another object of the present invention is to provide a semiconductor memory device which enables to write data to a cell by the bit group.
In order to solve the above problems, a semiconductor memory device having a burst mode in which a plurality of bits of data are transferred consecutively in response to an external command is provided by the present invention. This semiconductor memory device comprises transfer means for transferring data in the burst mode, transferred number setting means for setting the number of the plurality of bits of data transferred in the burst mode, write command input means for receiving an input write command, timing means for measuring time which has elapsed after the write command being input, and write start time setting means for setting time which elapses before the writing of data being begun, according to the number of bits of data set by the transferred number setting means.
In order to solve the above problems, a semiconductor memory device with a plurality of banks having a burst transfer mode in which a plurality of bits of data in a predetermined bank are accessed consecutively by inputting a single command is also provided by the present invention. This semiconductor memory device comprises command input means for receiving the command input, bank selection means for selecting a predetermined bank corresponding to the command, burst transfer means for performing a burst transfer with a bank selected by the bank selection means as a target, and command input prohibition means for prohibiting the command input means from receiving a new command input in the case of a burst transfer being begun by the burst transfer means.
In order to solve the above problems, a semiconductor memory device having a burst transfer mode in which a plurality of bits of data are transferred consecutively by specifying one address is also provided by the present invention. This semiconductor memory device comprises address input means for receiving the address input, data input means for receiving the plurality of bits of data input, burst transfer means for performing a burst transfer of the plurality of bits of data input via the data input means to a cell area corresponding to the address input via the address input means, burst transfer length specifying means for receiving transfer length specified by the burst transfer means, and data input limiting means for limiting data input from the data input means in the case of a burst transfer length of xe2x80x9c0xe2x80x9d being specified by the burst transfer length specifying means.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.